SN74SSTV16857 Datasheet, PDF (1/9 Pages) Texas Instruments – 14-BIT REGISTERED BUFFER WITH SSTL 2 INPUTS AND OUTPUTS

SN74SSTV16857
14ĆBIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
D Member of the Texas Instruments
Widebus Family
D Supports SSTL_2 Data Inputs
D Outputs Meet SSTL_2 Class II
Specifications
D Differential Clock (CLK and CLK) Inputs
D Supports LVCMOS Switching Levels on the
RESET Input
D RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
This 14-bit registered buffer is designed for 2.3-V
to 2.7-V V_CC operation.
All inputs are SSTL_2, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II
compatible.
DGG PACKAGE
(TOP VIEW)
Q1 1
Q2 2
GND 3
V_DDQ 4
Q3 5
Q4 6
Q5 7
GND 8
V_DDQ 9
Q6 10
Q7 11
V_DDQ 12
GND 13
Q8 14
Q9 15
V_DDQ 16
GND 17
Q10 18
Q11 19
Q12 20
V_DDQ 21
GND 22
Q13 23
Q14 24
48 D1
47 D2
46 GND
45 V_CC
44 D3
43 D4
42 D5
41 D6
40 D7
39 CLK
38 CLK
37 V_CC
36 GND
35 V_REF
34 RESET
33 D8
32 D9
31 D10
30 D11
29 D12
28 V_CC
27 GND
26 D13
25 D14
The SN74SSTV16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 70°C TSSOP – DGG Tape and reel SN74SSTV16857DGGR SSTV16857
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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