SN74SSTU32864 Datasheet, PDF (1/18 Pages) Texas Instruments – 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS

SN74SSTU32864
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
SCES434 – MARCH 2003
D Member of the Texas Instruments
Widebus+ Family
D Pinout Optimizes DDR-II DIMM PCB Layout
D Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer
D Chip-Select Inputs Gate the Data Outputs
from Changing State and Minimizes System
Power Consumption
D Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
D Supports SSTL_18 Data Inputs
D Differential Clock (CLK and CLK) Inputs
D Supports LVCMOS Switching Levels on the
Control and RESET Inputs
D RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 5000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V_CC operation. In the
1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.
The SN74SSTU32864 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to
register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low)
to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired
to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration,
the A6, D6, and H6 terminals are driven low and should not be used.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs always
must be held at a valid logic high or low level.
The two V_REF pins (A3 and T3), are connected together internally by approximately 150 Ω. However, it is
necessary to connect only one of the two V_REF pins to the external V_REF power supply. An unused V_REF pin
should be terminated with a V_REF coupling capacitor.
ORDERING INFORMATION
TA
PACKAGE^†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 70°C LFBGA – GKE Tape and reel SN74SSTU32864GKER SU864
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2003, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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