SN74SSTE32882 Datasheet, PDF (1/7 Pages) Texas Instruments – 28-Bit to 56-Bit Registered Buffer With Address Parity Test and One Pair to Four Pair Differential Clock PLL Driver

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SN74SSTE32882
SCAS840 – NOVEMBER 2006
28-Bit to 56-Bit Registered Buffer With Address Parity Test and One Pair to Four Pair
Differential Clock PLL Driver
FEATURES
• Pinout Optimizes DDR3 DIMM PCB Layout
• 1-to-2 Register Outputs and 1-to-4 Clock Pair
Outputs Support Stacked DDR3 DIMMs
• Chip-Select Inputs Gate the Data Outputs
from Changing State and Minimizes System
Power Consumption
• Supports SSTL_15 Data Inputs
• Checks Parity on Command and Address
(CS-gated) Data Inputs
• 1.5-V Phase Lock Loop Clock Driver for
Buffering One Differential Clock Pair (CK and
CK) and Distributing to Four Differential
Outputs
• Supports LVCMOS Levels on RESET Input
• RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low, Except QERR
APPLICATIONS
• DDR3 RDIMM
DESCRIPTION
This 28-bit 1:2 configurable registered buffer is designed for 1.425-V to 1.575-V V_CC operation. One device per
DIMM is required to drive up to 36 SDRAM loads (maximum 2 Ranks × 4).
The SN74SSTE32882 includes a high-performance, low-jitter, low-skew PLL based clock buffer that distributes a
differential input clock signal (CK and CK) to four differential pairs of clock outputs (QCKn and QCKn) and to
one differential pair of feedback clock outputs (FBOUT and FBOUT). The clock outputs are controlled by the
input clocks (CK and CK), the feedback clocks (FBIN and FBIN) and the analog power inputs (AV_DD and AV_SS).
The SN74SSTE32882 is able to track spread spectrum clocking (SSC) for reduced EMI.
All device inputs are SSTL_15, except reset (RESET), which is LVCMOS. All outputs are edge-controlled circuits
optimized for terminated DIMM loads, and meet SSTL_15 specifications at the DRAM inputs, except the
open-drain error (QERR) output. The clock outputs (Yn, Yn) and control outputs (QACSn, QBCSn, QACKEn,
QBCKEn, QAODTn and QBODTn) are designed with different drive strengths, from the other data Qn outputs,
to adapt to different loading conditions.
The SN74SSTE32882 operates from the differential clock (CK and CK). Data are registered at the crossing of
CK going high and CK going low.
The SN74SSTE32882 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input and
compares it with the data received on the DCSn gated D-inputs (DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE)
during the previous clock cycle. The convention is even parity, i.e., valid parity is defined as an even number of
ones across the DCSn gated D-inputs combined with the parity input bit. For correct operation, all DCSn gated
D-inputs must be tied to corresponding outputs of the memory controller used for parity generation. Parity errors
are flagged on the open-drain QERR pin (active low).
ORDERING INFORMATION
T_X
TBD
PACKAGE ⁽¹⁾
XXXX –ZAL
Tape and reel
ORDERABLE PART NUMBER
SN74SSTE32882ZALR
TOP-SIDE MARKING
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2006, Texas Instruments Incorporated