SN74SSQEA32882 Datasheet, PDF (1/6 Pages) Texas Instruments – 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER

SN74SSQEA32882
www.ti.com...................................................................................................................................................................................................... SCAS879 – JUNE 2009
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST
ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER
FEATURES
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• JEDEC SSTE32882 Compliant
• 1-to-2 Register Outputs and 1-to-4 Clock Pair
Outputs Support Stacked DDR3 DIMMs
• CKE Powerdown mode for optimized system
power consumption
• 1.5V/1.35V Phase Lock Loop Clock Driver
Buffers One Differential Clock Pair (CK and
CK) and Distributes to Four Differential
Outputs
• 1.5V/1.35V CMOS Inputs
• Checks Parity on Command and Address
(CS-gated) Data Inputs
• Supports Four Chip Selects
• Configurable Driver Strength
APPLICATIONS
• DDR3 Registered DIMMs up to DDR3-1600
• DDR3L Registered DIMMs up to DDR3L-1333
• Single-, Dual- and Quad-Rank RDIMM
DESCRIPTION/ORDERING INFORMATION
This JEDEC SSTE32882-compliant, 28-bit 1:2 or
26-bit 1:2 and 4-bit 1:1 registering clock driver with
parity is designed for operation on DDR3 registered
DIMMs with with V_DD of 1.5 V and on DDR3L
registered DIMMs with V_DD of 1.35 V.
The SN74SSQEA32882 implements different
power-saving mechanisms to reduce thermal power
dissipation and to support system power-down states.
Power consumption is further reduced by disabling
unused outputs.
All inputs are 1.5V and 1.35V CMOS-compatible. All
outputs are optimized to drive DRAM signals on
terminated traces in DDR3 RDIMM applications.
Clock outputs Yn and Yn and control net outputs
DxCKEn, DxCSn, and DxODTn can each be driven
with a different strength and skew to optimize signal
integrity, compensate for different loading, and
balance signal travel speed.
The SN74SSQEA32882 has two basic modes of
operation associated with the Quad Chip Select
Enable (QCSEN) input.
First, when the QCSEN input pin is open or pulled
high, the component has two chip select inputs,
DCS0 and DCS1, and two copies of each chip select
output, QACS0, QACS1, QBCS0 and QBCS1. This
mode is the QuadCS disabled mode. Alternatively,
when the QCSEN input pin is pulled low, the
component has four chip select inputs DCS[3:0], and
four chip select outputs, QCS[3:0]. This mode is the
QuadCS enabled mode.
When QCSEN is high or floating, the device also
supports an operating mode that allows a single
device to be mounted on the back side of a DIMM
array. This device can then be configured to keep the
input bus termination (IBT) feature enabled for all
input signals independent of MIRROR. The
SN74SSQEA32882. operates from a differential clock
(CK and CK). Data are registered at the crossing of
CK going high and CK going low. This data can either
be re-driven to the outputs or used to access internal
control registers. Details are covered in the Function
Tables (each flip-flop) with QCSEN = low.
Input bus data integrity is protected by a parity
function. All address and command input signals are
summed; the last bit of the sum is then compared to
the parity signal delivered by the system at the
PAR_IN input one clock cycle later. If these two
values do not match, the device pulls the open drain
output ERROUT low. The control signals (DCKE0,
DCKE1, DODT0, DODT1, and DCS[n:0]) are not part
of this computation.
The package design is optimal for high-density
DIMMs. By aligning input and output positions
towards DIMM finger-signal ordering and SDRAM
ballout, the device de-scrambles the DIMM traces
and allows low crosstalk designs with low
interconnect latency. Edge-controlled outputs reduce
ringing and improve signal eye opening at the
SDRAM inputs.
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated