SN74S225 Datasheet, PDF (1/10 Pages) Texas Instruments – 16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS

SN74S225
16 × 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
WITH 3-STATE OUTPUTS
SDLS207B – SEPTEMBER 1976 – REVISED APRIL 1998
D Independent Asychronous Inputs and
Outputs
D 16 Words by 5 Bits
D DC to 10-MHz Data Rate
D 3-State Outputs
D Packaged in Standard Plastic 300-mil DIPs
description
This 80-bit active-element memory is a monolithic
Schottky-clamped transistor-transistor logic
(STTL) array organized as 16 words by 5 bits. A
memory system using the SN74S225 easily can
be expanded in multiples of 48 words or of 10 bits
as shown in Figure 3. The 3-state outputs
controlled by a single output-enable (OE) input
make bus connection and multiplexing easy.
N PACKAGE
(TOP VIEW)
CLKA 1
IR 2
UNCK OUT 3
D0 4
D1 5
D2 6
D3 7
D4 8
OE 9
GND ¹⁰
20 V_CC
19 CLKB
18 CLR
17 OR
16 UNCK IN
15 Q0
14 Q1
13 Q2
12 Q3
11 _Q4
A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array
at independent data rates. This FIFO is designed to process data at rates from dc to 10 MHz in a bit-parallel
format, word by word.
Reading or writing is done independently, utilizing separate asynchronous data clocks. Data can be written into
the array on the low-to-high transition of either load-clock (CLKA, CLKB) input. Data can be read out of the array
on the low-to-high transition of the unload-clock (UNCK IN) input (normally high). Writing data into the FIFO can
be accomplished in one of two ways:
D In applications not requiring a gated clock control, best results are achieved by applying the clock input to
one of the clocks while tying the other clock input high.
D In applications needing a gated clock, the load clock (gate control) must be high for the FIFO to load on the
next clock pulse.
CLKA and CLKB can be used interchangeably for either clock gate control or clock input.
Status of the SN74S225 is provided by three outputs. The input-ready (IR) output monitors the status of the last
word location and signifies when the memory is full. This output is high whenever the memory is available to
accept any data. The unload-clock (UNCK OUT) output also monitors the last word location. This output
generates a low-logic-level pulse (synchronized to the internal clock pulse) when the location is vacant. The third
status output, output ready (OR), is high when the first word location contains valid data and UNCK IN is high.
When UNCK IN goes low, OR will go low and stay low until new valid data is in the first word position. The first
word location is defined as the location from which data is provided to the outputs.
The data outputs are noninverted with respect to the data inputs and are 3-state, with a common control input
(OE). When OE is low, the data outputs are enabled to function as totem-pole outputs. A high logic level forces
each data output to a high-impedance state while all other inputs and outputs remain active.The clear (CLR)
input invalidates all data stored in the memory array by clearing the control logic and setting OR to a low logic
level on the high-to-low transition of a low-active pulse.
The SN74S225 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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