SN74S1051 Datasheet, PDF (1/13 Pages) Texas Instruments – 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY

D Designed to Reduce Reflection Noise
D Repetitive Peak Forward Current to 200 mA
D 12-Bit Array Structure Suited for
Bus-Oriented Systems
description/ordering information
This Schottky barrier diode bus-termination array
is designed to reduce reflection noise on memory
bus lines. This device consists of a 12-bit
high-speed Schottky diode array suitable for
clamping to V_CC and/or GND.
SN74S1051
12-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003
D, N, NS, OR PW PACKAGE
(TOP VIEW)
V_CC 1
D01 2
D02 3
D03 4
D04 5
D05 6
D06 7
GND 8
16 V_CC
15 D12
14 D11
13 D10
12 D09
11 D08
10 D07
9 GND
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74S1051N
SN74S1051N
0°C to 70°C
SOIC – D
Tube
Tape and reel
SN74S1051D
SN74S1051DR
S1051
SOP – NS
Tape and reel
SN74S1051NSR
74S1051
TSSOP – PW
Tape and reel
SN74S1051PWR
S1051
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
schematic diagrams
D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12
2
3
4
5
6
7 10 11 12 13 14 15
VCC VCC
1
16
8
9
GND GND
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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