SN74LVT240A Datasheet, PDF (1/13 Pages) Texas Instruments – 3.3-V ABT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS

D Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With 3.3-V
V_CC )
D Supports Unregulated Battery Operation
Down To 2.7 V
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D I_off and Power-Up 3-State Support Hot
Insertion
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN74LVT240A
3.3ĆV ABT OCTAL BUFFER/DRIVER
WITH 3ĆSTATE OUTPUTS
SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004
DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
1OE ₁
1A1 ₂
2Y4 3
1A2 4
2Y3 5
1A3 6
2Y2 7
1A4 8
2Y1 9
GND 10
20 ^V_CC
19 ^2OE
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11 2A1
description/ordering information
This octal buffer and line driver is designed specifically for low-voltage (3.3-V) V_CC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When
OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
When V_CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V_CC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − DW
Tube
Tape and reel
SN74LVT240ADW
SN74LVT240ADWR
LVT240A
SOP − NS
Tape and reel SN74LVT240ANSR
LVT240A
−40°C to 85°C
SSOP − DB
TSSOP − PW
Tape and reel
Tube
Tape and reel
SN74LVT240ADBR
SN74LVT240APW
SN74LVT240APWR
LX240A
LX240A
TVSOP − DGV Tape and reel SN74LVT240ADGVR
LX240A
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2004, Texas Instruments Incorporated
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