SN74LVT16835 Datasheet, PDF (1/7 Pages) Texas Instruments – 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

SN74LVT16835
3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996
D State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
D Member of the Texas Instruments
Widebus ™ Family
D Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V_CC)
D Supports Unregulated Battery Operation
Down to 2.7 V
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Supports Live Insertion
D Distributed V_CC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D Flow-Through Architecture Optimizes
PCB Layout
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages Using 25-mil
Center-to-Center Spacings
description
The SN74LVT16835 is an 18-bit universal bus
driver designed for low-voltage (3.3-V) V_CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
DGG OR DL PACKAGE
(TOP VIEW)
NC 1
NC 2
Y1 3
GND 4
Y2 5
Y3 6
V_CC 7
Y4 8
Y5 9
Y6 10
GND 11
Y7 12
Y8 13
Y9 14
Y10 15
Y11 16
Y12 17
GND 18
Y13 19
Y14 20
Y15 21
V_CC 22
Y16 23
Y17 24
GND 25
Y18 26
OE 27
LE 28
56 GND
55 NC
54 A1
53 GND
52 A2
51 A3
50 V_CC
49 A4
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
39 GND
38 A13
37 A14
36 A15
35 V_CC
34 A16
33 A17
32 GND
31 A18
30 CLK
29 GND
NC – No internal connection
Data flow from A to Y is controlled by the
output-enable (OE) input. This device operates in
the transparent mode when the latch-enable (LE)
input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the
A-bus data is stored in the latch/flip-flop on the low-to-high transition of the clock. When OE is high, the outputs
are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT16835 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the input/output (I/O) pins and functionality of standard small-outline packages in the same
printed circuit board area.
The SN74LVT16835 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
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