SN74LVT16240 Datasheet, PDF (1/11 Pages) Texas Instruments – 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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FEATURES
• Members of the Texas Instruments Widebus™
Family
• State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
• Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC)
• Support Unregulated Battery Operation Down
to 2.7 V
• Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 3.3 V, T_A = 25°C
• I_off and Power-Up 3-State Support Hot
Insertion
• Distributed V_CC and GND Pins Minimize
High-Speed Switching Noise
• Flow-Through Architecture Optimizes PCB
Layout
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
• Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package Using
25-mil Center-to-Center Spacings
SN54LVT16240, SN74LVT16240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS717A – APRIL 2000 – REVISED NOVEMBER 2006
SN54LVT16240 . . . WD PACKAGE
SN74LVT16240 . . . DGG OR DL PACKAGE
(TOP VIEW)
1OE 1
1Y1 2
1Y2 3
GND 4
1Y3 5
1Y4 6
V_CC 7
2Y1 8
2Y2 9
GND 10
2Y3 11
2Y4 12
3Y1 13
3Y2 14
GND 15
3Y3 16
3Y4 17
V_CC 18
4Y1 19
4Y2 20
GND 21
4Y3 22
4Y4 23
4OE 24
48 2OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 V_CC
41 2A1
40 2A2
39 GND
38 2A3
37 2A4
36 3A1
35 3A2
34 GND
33 3A3
32 3A4
31 V_CC
30 4A1
29 4A2
28 GND
27 4A3
26 4A4
25 3OE
DESCRIPTION/ORDERING INFORMATION
The 'LVT16240 devices are 16-bit buffers and line drivers designed specifically for low-voltage (3.3-V) V_CC
operation, but with the capability to provide a TTL interface to a 5-V system environment.
These devices are designed specifically to improve both the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide
inverting outputs and symmetrical active-low output-enable (OE) inputs.
When V_CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V_CC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2006, Texas Instruments Incorporated