SN74LVC843A Datasheet, PDF (1/10 Pages) Texas Instruments – 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
D Power Off Disables Outputs, Permitting
Live Insertion
D Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V_CC)
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
SN74LVC843A
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS308E – MARCH 1993 – REVISED JUNE 1998
DB, DW, OR PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
9D 10
CLR 11
GND 12
24 V_CC
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 9Q
14 PRE
13 LE
description
This 9-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V V_CC operation.
The SN74LVC843A is designed specifically for driving highly capacitive or relatively low-impedance loads. It
is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.
The nine latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true
data at its outputs.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up
and power-down conditions. The outputs remain in the high-impedance state while the device is powered down.
In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVC843A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright © 1998, Texas Instruments Incorporated
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