SN74LVC821A_08 Datasheet, PDF (1/16 Pages) Texas Instruments – 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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FEATURES
• Operates From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 7.3 ns at 3.3 V
• Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
• Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V V_CC)
• I_off Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS304J – MARCH 1993 – REVISED FEBRUARY 2005
DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
9D 10
10D 11
GND 12
24 V_CC
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 9Q
14 10Q
13 CLK
DESCRIPTION/ORDERING INFORMATION
This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V V_CC operation.
The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working registers.
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the
device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
T_A
–40°C to 85°C
SOIC – DW
SOP – NS
SSOP – DB
TSSOP – PW
TVSOP – DGV
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
Tube of 25
SN74LVC821ADW
Reel of 2000
SN74LVC821ADWR
Reel of 2000
SN74LVC821ANSR
Reel of 2000
SN74LVC821ADBR
Tube of 60
SN74LVC821APW
Reel of 2000
SN74LVC821APWR
Reel of 250
SN74LVC821APWT
Reel of 2000
SN74LVC821ADGVR
TOP-SIDE MARKING
LVC821A
LVC821A
LC821A
LC821A
LC821A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated