SN74LVC821A Datasheet, PDF (1/9 Pages) Texas Instruments – 10-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
D Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V_CC)
D Power Off Disables Outputs, Permitting
Live Insertion
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
SN74LVC821A
10-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS304F – MARCH 1993 – REVISED JUNE 1998
DB, DW, OR PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
9D 10
10D 11
GND 12
24 V_CC
23 1Q
22 2Q
21 3Q
20 4Q
19 5Q
18 6Q
17 7Q
16 8Q
15 9Q
14 10Q
13 CLK
description
This 10-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V V_CC operation.
The SN74LVC821A features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports,
bidirectional bus drivers with parity, and working registers.
The ten flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the
device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVC821A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
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