SN74LVC573A-Q1 Datasheet, PDF (1/8 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCH

D Qualification in Accordance With
AEC-Q100^†
D Qualified for Automotive Applications
D Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Operates From 2 V to 3.6 V
D Inputs Accept Voltages to 5.5 V
D Max t_pd of 6.9 ns at 3.3 V
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
† _{Contact factory for details. Q100 qualification data available on}
request.
SN74LVC573AĆQ1
OCTAL TRANSPARENT DĆTYPE LATCH
WITH 3ĆSTATE OUTPUTS
SCAS714A − SEPTEMBER 2003 − REVISED MAY 2004
D Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V_CC)
D I_off Supports Partial-Power-Down Mode
Operation
DW OR PW PACKAGE
(TOP VIEW)
OE 1
1D 2
2D 3
3D 4
4D 5
5D 6
6D 7
7D 8
8D 9
GND 10
20 V_CC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
description/ordering information
The SN74LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V V_CC operation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the logic levels at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − DW
−40°C to 125°C
TSSOP − PW
Reel of 2000
Reel of 2000
SN74LVC573AQDWRQ1 L573AQ1
SN74LVC573AQPWRQ1 L573AQ1
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2004, Texas Instruments Incorporated
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