SN74LVC4245A-EP Datasheet, PDF (1/13 Pages) Texas Instruments – OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS

SN74LVC4245AĆEP
OCTAL BUS TRANSCEIVER AND 3.3ĆV TO 5ĆV SHIFTER
WITH 3ĆSTATE OUTPUTS
SCAS742 − DECEMBER 2003
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D Bidirectional Voltage Translator
D 5.5 V on A Port and 2.7 V to 3.6 V on B Port
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
(5 V) V_CCA 1
DIR 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 ¹⁰
GND 11
GND 12
24 V_CCB (3.3 V)
23 V_CCB (3.3 V)
22 OE
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 _B7
14 B8
13 GND
description/ordering information
This 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has V_CCB, which is set
at 3.3 V, and A port has V_CCA, which is set at 5 V. This allows for translation from a 3.3-V to a 5-V environment,
and vice versa.
The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin ’245 device
without board re-layout. The designer uses the data paths for pins 2−11 and 14−23 of the SN74LVC4245A to
align with the conventional ’245 pinout.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C TSSOP − PW Reel of 2000 SN74LVC4245AIPWREP C4245AEP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OE DIR
OPERATION
L
L
B data to A bus
L
H A data to B bus
H
X
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2003, Texas Instruments Incorporated
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