SN74LVC2G80 Datasheet, PDF (1/13 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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FEATURES
• Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.2 ns at 3.3 V
• Low Power Consumption, 10-µA Max I_CC
• Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Feature Supports Partial-Power-Down
Mode Operation
• Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN74LVC2G80
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES309C – DECEMBER 2001 – REVISED JUNE 2005
DCT OR DCU PACKAGE
(TOP VIEW)
1CLK 1
1D 2
2Q 3
GND 4
8 V_CC
7 1Q
6 2D
5 2CLK
YEP OR YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 2CLK
2Q 3 6 2D
1D 2 7 1Q
1CLK 1 8 V_CC
DESCRIPTION/ORDERING INFORMATION
This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting
the levels at the outputs.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T_A
PACKAGE ⁽¹⁾
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
–40°C to 85°C _{0.23-mm Large Bump – YZP (Pb-free)}
Tape and reel
ORDERABLE PART NUMBER
SN74LVC2G80YEPR
SN74LVC2G80YZPR
SSOP – DCT
Tape and reel SN74LVC2G80DCTR
VSSOP – DCU
Tape and reel SN74LVC2G80DCUR
TOP-SIDE MARKING⁽²⁾
_ _ _CX_
C80_ _ _
C80_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2005, Texas Instruments Incorporated