SN74LVC2G132 Datasheet, PDF (1/13 Pages) Texas Instruments – DUAL 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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FEATURES
• Available in Texas Instruments NanoStar™
and NanoFree™ Packages
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 5.3 ns at 3.3 V
• Low Power Consumption, 10-µA Max I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) >2 V at
V_CC = 3.3 V, T_A = 25°C
• I_off Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN74LVC2G132
DUAL 2-INPUT NAND GATE
WITH SCHMITT-TRIGGER INPUTS
SCES547A – FEBRUARY 2004 – REVISED JUNE 2005
DCT OR DCU PACKAGE
(TOP VIEW)
1A 1
1B 2
2Y 3
GND 4
8 V_CC
7 1Y
6 2B
5 2A
YEP OR YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 2A
2Y 3 6 2B
1B 2 7 1Y
1A 1 8 V_CC
DESCRIPTION/ORDERING INFORMATION
This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V V_CC operation.
The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive
logic. The device functions as two independent inverters, but because of Schmitt action, it has different input
threshold levels for positive-going (V_T+) and negative-going (V_T-) signals.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
ORDERING INFORMATION
T_A
–40°C to 85°C
PACKAGE ⁽¹⁾
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
ORDERABLE PART NUMBER
SN74LVC2G132YEPR
Reel of 3000
SN74LVC2G132YZPR
SSOP – DCT
Reel of 3000 SN74LVC2G132DCTR
VSSOP – DCU
Reel of 3000 SN74LVC2G132DCUR
Reel of 250 SN74LVC2G132DCUT
TOP-SIDE MARKING⁽²⁾
_ _ _D5_
C3B_ _ _
C3B_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated