SN74LVC2G126_08 Datasheet, PDF (1/12 Pages) Texas Instruments – DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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FEATURES
• Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4 ns at 3.3 V
• Low Power Consumption, 10-µA Max I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
DCT PACKAGE
(TOP VIEW)
1OE
1
1A
2
2Y
3
GND
4
8
V_CC
7
2OE
6
1Y
5
2A
SN74LVC2G126
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES205J – APRIL 1999 – REVISED JANUARY 2007
• I_off Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCU PACKAGE
(TOP VIEW)
1OE 1
8
1A 2
7
2Y 3
6
GND 4
5
V_CC
2OE
1Y
2A
YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 2A
2Y 3 6 1Y
1A 2 7 2OE
1OE 1 8 ^VCC
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual bus buffer gate is designed for 1.65-V to 5.5-V V_CC operation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER TOP-SIDE MARKING⁽²⁾
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74LVC2G126YZPR
_ _ _CN_
SSOP – DCT
Reel of 3000 SN74LVC2G126DCTR
C26_ _ _
VSSOP – DCU
Reel of 3000
Reel of 250
SN74LVC2G126DCUR
SN74LVC2G126DCUT
C26_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2007, Texas Instruments Incorporated