SN74LVC2G04_07 Datasheet, PDF (1/15 Pages) Texas Instruments – DUAL INVERTER GATE

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SN74LVC2G04
DUAL INVERTER GATE
SCES195L – APRIL 1999 – REVISED JANUARY 2007
FEATURES
• Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.1 ns at 3.3 V
• Low Power Consumption, 10-µA Max I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce) <0.8 V
at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) >2 V at
V_CC = 3.3 V, T_A = 25°C
• I_off Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
1A
1
GND
2
1A
1
6 1Y
1A 1 6 1Y
2A ^{3 4} 2Y
6
5
1Y
GND
V_CC
2A
2
3
5
V_CC
GND 2
2A 3
5 V_CC
4 2Y
GND ^{2 5 V}CC
1A ^{1 6} 1Y
4 2Y
2A
3
4
2Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual inverter is designed for 1.65-V to 5.5-V V_CC operation. The SN74LVC2G04 performs the Boolean
function Y = A.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T_A
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
Reel of 3000 SN74LVC2G04YZPR
–40°C to 85°C ^{SOT (SOT-23) – DBV}
Reel of 3000
Reel of 250
SN74LVC2G04DBVR
SN74LVC2G04DBVT
SOT (SC-70) – DCK
Reel of 3000
Reel of 250
SN74LVC2G04DCKR
SN74LVC2G04DCKT
SOT (SOT-563) – DRL
Reel of 4000 SN74LVC2G04DRLR
TOP-SIDE MARKING⁽²⁾
_ _ _CC_
C04_
CC_
CC_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2007, Texas Instruments Incorporated