SN74LVC1G373 Datasheet, PDF (1/13 Pages) Texas Instruments – SINGLE D-TYPE LATCH

D Available in the Texas Instruments
NanoStar and NanoFree Packages
D Supports 5-V V_CC Operation
D Inputs Accept Voltages to 5.5 V
D Max t_pd of 4 ns at 3.3 V
D Low Power Consumption, 10-µA Max I_CC
D ±24-mA Output Drive at 3.3 V
D I_off Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN74LVC1G373
SINGLE DĆTYPE LATCH
WITH 3ĆSTATE OUTPUT
SCES528A − DECEMBER 2003 − REVISED JUNE 2004
DBV OR DCK PACKAGE
(TOP VIEW)
LE 1
GND 2
D3
6 OE
5 V_CC
4Q
YEP OR YZP PACKAGE
(BOTTOM VIEW)
D 34 Q
GND 2 5 V_CC
LE 1 6 OE
description/ordering information
This single D-type latch is designed for 1.65-V to 5.5-V V_CC operation.
The SN74LVC1G373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
While the latch-enable (LE) input is high, the Q output follows the data (D) input. When LE is taken low, the Q
output is latched at the logic level set up at the D input.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
−40°C to 85°C
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SOT (SOT-23) − DBV
Reel of 3000
Reel of 3000
Reel of 250
SN74LVC1G373YEPR
SN74LVC1G373YZPR
SN74LVC1G373DBVR
SN74LVC1G373DBVT
_ _ _D3_
CA3_
SOT (SC-70) − DCK
Reel of 3000 SN74LVC1G373DCKR
D3_
Reel of 250 SN74LVC1G373DCKT
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at}
www.ti.com/sc/package.
‡ _{DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.}
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2004, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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