SN74LVC1G132_08 Datasheet, PDF (1/15 Pages) Texas Instruments – SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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SN74LVC1G132
SINGLE 2-INPUT NAND GATE
WITH SCHMITT-TRIGGER INPUTS
SCES546B – FEBRUARY 2004 – REVISED SEPTEMBER 2006
FEATURES
• Available in Texas Instruments NanoStar™
and NanoFree™ Packages
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 5.3 ns at 3.3 V
• Low Power Consumption, 10-µA Max I_CC
• ±24-mA Output Drive at 3.3 V
• I_off Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
A
1
B
2
5
V_CC
A
1
5
V_CC
B
2
GND
3
4Y
GND ^{3 4} Y
B²
A ^{1 5 V}_CC
GND
3
4
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The SN74LVC1G132 contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V
V_CC operation and performs the Boolean function Y = A • B or Y = A + B in positive logic.
Because of Schmitt action, this device has different input threshold levels for positive-going (V_T+) and
negative-going (V_T–) signals.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
T_A
–40°C to 85°C
PACKAGE ⁽¹⁾
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
SOT (SOT-23) – DBV
Reel of 3000
ORDERABLE PART NUMBER
SN74LVC1G132YEPR
SN74LVC1G132YZPR
Reel of 3000
Reel of 250
SN74LVC1G132DBVR
SN74LVC1G132DBVT
SOT (SC-70) – DCK
Reel of 3000
Reel of 250
SN74LVC1G132DCKR
SN74LVC1G132DCKT
TOP-SIDE MARKING⁽²⁾
_ _ _D5_
C3B_
D5_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2006, Texas Instruments Incorporated