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SN74LVC1G126 Datasheet, PDF (1/8 Pages) Texas Instruments – SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D Ioff Feature Supports Partial-Power-Down
Mode Operation
D Supports 5-V VCC Operation
D Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES224C – APRIL 1999 – REVISED FEBRUARY 2000
DBV OR DCK PACKAGE
(TOP VIEW)
OE 1
A2
GND 3
5 VCC
4Y
description
This single bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G126 is a single bus driver/line driver with a 3-state output. The output is disabled when the
output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G126 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE
A
OUTPUT
Y
H
H
H
H
L
L
L
X
Z
logic symbol†
1
OE
EN
2
A
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
Y
logic diagram (positive logic)
1
OE
2
A
4
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright © 2000, Texas Instruments Incorporated
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