SN74LVC1G125 Datasheet, PDF (1/8 Pages) Texas Instruments – SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

D EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
D I_off Feature Supports Partial-Power-Down
Mode Operation
D Supports 5-V V_CC Operation
D Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
SN74LVC1G125
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES223C – APRIL 1999 – REVISED FEBRUARY 2000
DBV OR DCK PACKAGE
(TOP VIEW)
OE 1
A2
GND 3
5 V_CC
4Y
description
This bus buffer gate is designed for 1.65-V to 5.5-V V_CC operation.
The SN74LVC1G125 features a single line driver with a 3-state output. The output is disabled when the
output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G125 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
logic symbol^†
1
OE
EN
2
A
† _{This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.}
4
Y
logic diagram (positive logic)
1
OE
2
A
4
Y
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PRODUCT PREVIEW information concerns products in the formative or
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specifications are design goals. Texas Instruments reserves the right to
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