SN74LVC1G08 Datasheet, PDF (1/16 Pages) Texas Instruments – SINGLE 2-INPUT POSITIVE-AND GATE

SN74LVC1G08
SINGLE 2ĆINPUT POSITIVEĆAND GATE
SCES217S − APRIL 1999 − REVISED JUNE 2005
D Available in the Texas Instruments
NanoStar and NanoFree Packages
D Supports 5-V V_CC Operation
D Inputs Accept Voltages to 5.5 V
D Max t_pd of 3.6 ns at 3.3 V
D Low Power Consumption, 10-µA Max I_CC
D ±24-mA Output Drive at 3.3 V
D I_off Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
A
1
B
2
5
V_CC
A
1
5
V_CC
B
2
A1
B2
5 V_CC GND ^{3 4 Y}
B²
GND 3 4 Y
A ^{1 5} V_CC
GND
3
4Y
GND
3
4
Y
See mechanical drawings for dimensions.
description/ordering information
The SN74LVC1G08 performs the Boolean function Y + A • B or Y + A ) B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74LVC1G08YEAR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Reel of 3000
SN74LVC1G08YZAR
SN74LVC1G08YEPR
_ _ _CE_
NanoFree − WCSP (DSBGA)
−40°C to 85°C _{0.23-mm Large Bump − YZP (Pb-free)}
SN74LVC1G08YZPR
SOT (SOT-23) − DBV
Reel of 3000
Reel of 250
SN74LVC1G08DBVR
SN74LVC1G08DBVT
C08_
SOT (SC-70) − DCK
Reel of 3000 SN74LVC1G08DCKR
Reel of 250
SN74LVC1G08DCKT _{CE_}
SOT (SOT-553) − DRL
Reel of 4000 SN74LVC1G08DRLR
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at}
www.ti.com/sc/package.
‡ _{DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.}
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2005, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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