SN74LVC1G00_101 Datasheet, PDF (1/16 Pages) Texas Instruments – SINGLE 2-INPUT POSITIVE-NAND GATE

SN74LVC1G00
www.ti.com
SCES212V – APRIL 1999 – REVISED FEBRUARY 2010
SINGLE 2-INPUT POSITIVE-NAND GATE
Check for Samples: SN74LVC1G00
FEATURES
1
• Available in the Texas Instruments NanoStar™
Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 3.8 ns at 3.3 V
• Low Power Consumption, 10-mA Max I_CC
• ±24-mA Output Drive at 3.3 V
• I_off Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
A
1
B
2
5
V_CC
A
1
5
V_CC
A1
5 V_CC
GND ^{3 4} Y
B
2
B2
GND 3
4Y
B²
A ¹⁵
V_CC
GND
3
4
Y
GND
3
4
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V V_CC operation.
The SN74LVC1G00 performs the Boolean function Y = A ● B or Y = A + B in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION⁽¹⁾
T_A
PACKAGE ⁽²⁾
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
ORDERABLE PART NUMBER
SN74LVC1G00YZPR
–40°C to 85°C ^{SOT (SOT-23) – DBV}
Reel of 3000 SN74LVC1G00DBVR
Reel of 250 SN74LVC1G00DBVT
SOT (SC-70) – DCK
Reel of 3000 SN74LVC1G00DCKR
Reel of 250 SN74LVC1G00DCKT
SOT (SOT-553) – DRL
Reel of 4000 SN74LVC1G00DRLR
TOP-SIDE MARKING⁽³⁾
_ _ _ CA_
C00_
CA_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ● = Pb-free).
1
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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