SN74LVC137A Datasheet, PDF (1/8 Pages) Texas Instruments – 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES

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FEATURES
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• Typical V_OLP (Output Ground Bounce)
< 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
> 2 V at V_CC = 3.3 V, T_A = 25°C
• Inputs Accept Voltages to 5.5 V
• Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline (DB),
and Thin Shrink Small-Outline (PW) Packages
SN74LVC137A
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
WITH ADDRESS LATCHES
SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005
D, DB, OR PW PACKAGE
(TOP VIEW)
A1
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
GND 8
16 V_CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
DESCRIPTION
This 3-line to 8-line decoder/demultiplexer, with latches on three address inputs, is designed for 1.65-V to 3.6-V
V_CC operation.
The SN74LVC137A is designed for high-performance memory-decoding or data-routing applications requiring
very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize
the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the
delay times of this decoder and the enable time of the memory usually are less than the typical access time of
the memory. This means that the effective system delay introduced by the decoder is negligible.
When the latch-enable (G2A) input is low, the SN74LVC137A acts as a decoder/demultiplexer. When G2A
transitions from low to high, the address present at the inputs (A, B, and C) is stored in the latches. Further
address changes are ignored, provided G2A remains high. The output-enable (G1 and G2B) inputs control the
outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2B is
high.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC137A is characterized for operation from –40°C to 85°C.
LATCH
ENABLE
G2A
X
X
L
L
L
L
L
L
L
L
H
INPUTS
OUTPUT
ENABLE
G1
G2B
C
X
H
X
L
X
X
H
L
L
H
L
L
H
L
L
H
L
L
H
L
H
H
L
H
H
L
H
H
L
H
H
L
X
SELECT
B
X
X
L
L
H
H
L
L
H
H
X
FUNCTION TABLE
OUTPUTS
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
H
H
H
H
H
H
H
X
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
X
Outputs corresponding to stored address = L; all other outputs = H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
PRODUCT PREVIEW information concerns products in the forma-
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
Copyright © 1994–2005, Texas Instruments Incorporated