SN74LVC112A Datasheet, PDF (1/13 Pages) Texas Instruments – DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

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FEATURES
• Operates From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.8 ns at 3.3 V
• Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN74LVC112A
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
SCAS289L – JANUARY 1993 – REVISED AUGUST 2005
D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1CLK 1
1K 2
1J 3
1PRE 4
1Q 5
1Q 6
2Q 7
GND 8
16 VCC
15 1CLR
14 2CLR
13 2CLK
12 2K
11 2J
10 2PRE
9 2Q
DESCRIPTION/ORDERING INFORMATION
This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V V_CC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time
requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can
perform as a toggle flip-flop by tying J and K high.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
Tube of 40 SN74LVC112AD
SOIC – D
Reel of 2500 SN74LVC112ADR
Reel of 250 SN74LVC112ADT
SOP – NS
Reel of 2000 SN74LVC112ANSR
SSOP – DB
Reel of 2000 SN74LVC112ADBR
Tube of 90 SN74LVC112APW
TSSOP – PW
Reel of 2000 SN74LVC112APWR
Reel of 250 SN74LVC112APWT
TVSOP – DGV
Reel of 2000 SN74LVC112ADGVR
TOP-SIDE MARKING
LVC112A
LVC112A
LC112A
LC112A
LC112A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated