SN74LV8151 Datasheet, PDF (1/14 Pages) Texas Instruments – 10-BIT UNIVERSAL SCHMITT-TRIGGER BUFFER WITH 3-STATE OUTPUTS

SN74LV8151
10ĆBIT UNIVERSAL SCHMITTĆTRIGGER BUFFER
WITH 3ĆSTATE OUTPUTS
SCES610 − OCTOBER 2004
D 2-V to 5.5-V V_CC Operation
D Max t_pd of 15 ns at 5 V
D Schmitt-Trigger Inputs Allow for Slow Input
Rise/Fall Time
D Polarity Control for Y Outputs Selects True
or Complementary Logic
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 3.3 V, T_A = 25°C
D I_off Supports Partial-Power-Down Mode
Operation
D Supports Mixed-Mode Voltage Operation on
All Ports
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
NT OR PW PACKAGE
(TOP VIEW)
T/C 1
A2
B3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
D8 11
GND 12
24 V_CC
23 P
22 N
21 Y1
20 Y2
19 Y3
18 Y4
17 Y5
16 Y6
15 Y7
14 Y8
13 OE
description/ordering information
The SN74LV8151 is a 10-bit universal Schmitt-trigger buffer with 3-state outputs, designed for 2-V to 5.5-V V_CC
operation. The logic control (T/C) pin allows the user to configure Y1 to Y8 as noninverting or inverting outputs.
When T/C is high, the Y outputs are noninverted (true logic ), and when T/C is low, the Y outputs are inverted
(complementary logic).
When output-enable (OE) input is low, the device passes data from Dn to Yn. When OE is high, the Y outputs
are in the high-impedance state. The path A to P is a simple Schmitt-trigger buffer, and the path B to N is a simple
Schmitt-trigger inverter.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − NT
Tube
SN74LV8151NT
SN74LV8151NT
−40°C to 85°C
TSSOP − PW
Tube
SN74LV8151PW
Tape and reel SN74LV8151PWR
LV8151
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2004, Texas Instruments Incorporated
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