SN74LV74A-Q1 Datasheet, PDF (1/10 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

SN74LV74AĆQ1
DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP
D Qualification in Accordance With
AEC-Q100^†
D Qualified for Automotive Applications
D Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
D 2-V to 5.5-V V_CC Operation
D Max t_pd of 13 ns at 5 V
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC = 3.3 V, T_A = 25°C
D Support Mixed-Mode Voltage Operation on
All Ports
D I_off Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
† _{Contact factory for details. Q100 qualification data available on}
request.
SCLS556A − DECEMBER 2003 − REVISED MAY 2004
D OR PW PACKAGE
(TOP VIEW)
1CLR 1
1D 2
1CLK 3
1PRE ⁴
1Q ⁵
1Q ⁶
GND ⁷
14 V_CC
13 2CLR
12 2D
11 _2CLK
10 _2PRE
9 _2Q
8 _2Q
description/ordering informationS
This dual positive-edge-triggered D-type flip-flop is designed for 2-V to 5.5-V V_CC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − D
−40°C to 125°C
TSSOP − PW
Tape and reel SN74LV74AQDRQ1
Tape and reel SN74LV74AQPWRQ1
LV74A
LV74A
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2004, Texas Instruments Incorporated
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