SN74LV161284 Datasheet, PDF (1/11 Pages) Texas Instruments – 19-BIT BUS INTERFACE

SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
D 4.5-V to 5.5-V V_CC Operation
D 1.4-kΩ Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors
D Designed for IEEE Std 1284-I (Level-1 Type)
and IEEE Std 1284-II (Level-2 Type)
Electrical Specifications
D Flow-Through Architecture Optimizes PCB
Layout
D Latch-Up Performance Exceeds 250 mA Per
JEDEC 17
D ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 300-V Machine Model (A115-A)
– 2000-V Charged-Device Model (C101)
description/ordering information
The SN74LV161284 is designed for 4.5-V to
5.5-V V_CC operation. This device provides
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
This device has eight bidirectional bits; data can
flow in the A-to-B direction when DIR is high, and
in the B-to-A direction when DIR is low. This
device also has five drivers, which drive the cable
side, and four receivers. The SN74LV161284 has
one receiver dedicated to the HOST LOGIC line
and a driver to drive the PERI LOGIC line.
DGG OR DL PACKAGE
(TOP VIEW)
HD 1
A9 2
A10 3
A11 4
A12 5
A13 6
V_CC 7
A1 8
A2 9
GND 10
A3 11
A4 12
A5 13
A6 14
GND 15
A7 16
A8 17
V_CC 18
PERI LOGIC IN 19
A14 20
A15 21
A16 22
A17 23
HOST LOGIC OUT 24
48 DIR
47 Y9
46 Y10
45 Y11
44 Y12
43 Y13
42 V_CC CABLE
41 B1
40 B2
39 GND
38 B3
37 B4
36 B5
35 B6
34 GND
33 B7
32 B8
31 V_CC CABLE
30 PERI LOGIC OUT
29 C14
28 C15
27 C16
26 C17
25 HOST LOGIC IN
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and
PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low.
This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II
(level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT,
all cable-side pins have a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated
output driver is in the low state or if the output voltage is above V_CC CABLE. If V_CC CABLE is off,
PERI LOGIC OUT is set to low.
The device has two supply voltages. V_CC is designed for 4.5-V to 5.5-V operation. V_CC CABLE supplies the
output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 85°C
SSOP – DL
Tube
Tape and reel
SN74LV161284DL
SN74LV161284DLR
LV161284
TSSOP – DGG
Tape and reel SN74LV161284DGGR LV161284
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2002, Texas Instruments Incorporated
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