SN74HSTL16919 Datasheet, PDF (1/8 Pages) Texas Instruments – 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH WITH INPUT PULLUP RESISTORS

SN74HSTL16919
9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
WITH INPUT PULLUP RESISTORS
SCES348 – MARCH 2001
D Member of Texas Instruments’ Widebus
Family
D Inputs Meet JEDEC HSTL Std JESD 8-6,
and Outputs Meet Level III Specifications
D 10-kΩ Pullup Resistor on Data and LE
Inputs
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description
This 9-bit to 18-bit D-type latch is designed for
3.15-V to 3.45-V V_CC operation. The D inputs
accept HSTL levels and the Q outputs provide
LVTTL levels.
The SN74HSTL16919 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of nine outputs is controlled with its
own latch-enable (LE) input.
Each of the nine D inputs is tied to the inputs of two
D-type latches that provide true data (Q) at the
outputs. While LE is low, the Q outputs of the
corresponding nine latches follow the D inputs.
When LE is taken high, the Q outputs are latched
at the levels set up at the D inputs.
DGG PACKAGE
(TOP VIEW)
2Q1 1
1Q1 2
GND 3
D1 4
D2 5
V_CC 6
D3 7
D4 8
GND 9
1LE 10
GND 11
V_REF 12
GND 13
2LE 14
GND 15
D5 16
D6 17
D7 18
V_CC 19
D8 20
D9 21
GND 22
2Q9 23
1Q9 24
48 V_CC
47 V_CC
46 1Q2
45 2Q2
44 GND
43 1Q3
42 2Q3
41 V_CC
40 1Q4
39 2Q4
38 GND
37 1Q5
36 2Q5
35 GND
34 1Q6
33 2Q6
32 V_CC
31 1Q7
30 2Q7
29 GND
28 1Q8
27 2Q8
26 V_CC
25 V_CC
To ensure low I_CC during power up or power down, 10-kΩ pullup resistors are included on the D and LE inputs
to ensure a differential voltage relative to V_REF. V_REF must be applied prior to or at the same time as V_CC, or
V_REF must be pulled down to ground.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 70°C TSSOP – DGG Tape and reel SN74HSTL16919DGGR HSTL16919
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design}
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2001, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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