SN74GTLPH16927 Datasheet, PDF (1/19 Pages) Texas Instruments – 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS

SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
D Member of the Texas Instruments
Widebus Family
D TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
D OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
D Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
D GTLP Buffered SYSCLK Signal (SSCLK) for
Source-Synchronous Applications
D LVTTL Interfaces Are 5-V Tolerant
D Medium-Drive GTLP Outputs (50 mA)
D LVTTL Outputs (–24 mA/24 mA)
D GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
D I_off, Power-Up 3-State, and BIAS V_CC
Support Live Insertion
D Bus Hold on A-Port Data Inputs
D Distributed V_CC and GND Pins Minimize
High-Speed Switching Noise
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
DGG OR DGV PACKAGE
(TOP VIEW)
DIR 1
OE 2
A1 3
GND 4
A2 5
A3 6
V_CC 7
A4 8
A5 9
A6 10
GND 11
A7 12
A8 13
A9 14
A10 15
A11 16
A12 17
GND 18
A13 19
A14 20
A15 21
V_CC 22
A16 23
A17 24
GND 25
A18 26
CLKOUT 27
CKOE 28
56 FSTA
55 BIAS V_CC
54 B1
53 GND
52 B2
51 B3
50 V_REF
49 B4
48 B5
47 B6
46 GND
45 B7
44 B8
43 B9
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
35 CMS
34 B16
33 B17
32 GND
31 B18
30 SSCLK
29 SYSCLK
The SN74GTLPH16927 is a medium-drive, 18-bit bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. The device allows for transparent and latched modes of data transfer.
Additionally, with the use of the clock-mode select (CMS) input, the device can be used in source-synchronous
and clock-synchronous applications. Source-synchronous applications require the skew between the clock
output and data output to be minimized for optimum maximum-frequency system performance. In order to
reduce this skew, a flexible setup-time adjustment (FSTA) feature is incorporated into the device that sets a
predetermined delay between the clock and data. The CMS and direction (DIR) inputs control the mode of the
device.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG Tape and reel SN74GTLPH16927GR
GTLPH16927
–40°C to 85°C TVSOP – DGV Tape and reel SN74GTLPH16927VR
GL927
VFBGA – GQL Tape and reel SN74GTLPH16927KR
GL927
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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