SN74GTLPH16612 Datasheet, PDF (1/11 Pages) Texas Instruments – 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER

SN74GTLPH16612
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
D Members of the Texas Instruments (TI™)
Widebus™ Family
D UBT ™ (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D Translate Between GTLP Signal Levels and
LVTTL Logic Levels
D Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
D B-Port Transition Time Optimized for
Distributed Backplane Loads
D I_off Supports Partial-Power-Down Mode
Operation
SCES326 – MARCH 2000
D Bus Hold on A-Port Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Distributed V_CC and GND Pins Minimize
High-Speed Switching Noise
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D Package Options Include Plastic Shrink
Small-Outline (DL), and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR.
description
The SN74GTLPH16612 is a medium-drive, 18-bit UBT (universal bus transceiver) that provides
LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or
clock-enabled modes of data transfer. This device provides a high-speed interface between cards operating at
LVTTL logic levels and backplanes operating at GTLP signal levels. High-speed (about two times faster than
standard LVTTL or TTL) backplane operation is a direct result of the reduced output swing (<1 V), reduced input
threshold levels, and OEC™ (output edge control ). These improvements minimize bus settling time and have
been designed and tested using several backplane models.
VTT
.25”
.875”
VTT
1.8
.25”
1.6
TI GTL16612
.625”
.625”
.625”
.625”
Conn.
Conn.
Conn.
Conn.
1”
Rcvr
Slot 1
1”
Rcvr
Slot 2
1”
Drvr
Slot 8
1”
Rcvr
Slot 16
1.4
1.2
1.0
0.8
0.6
0.4
0
Fairchild GTLP16612
TI GTLPH16612
10
20
30
t – Time – ns
Figure 1. Test Backplane Model With Output Waveform Results
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI, OEC, UBT, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1