SN74GTLPH1655 Datasheet, PDF (1/16 Pages) Texas Instruments – 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER

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SN74GTLPH1655
16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE
UNIVERSAL BUS TRANSCEIVER
SCES294C – OCTOBER 1999 – REVISED MAY 2005
FEATURES
• Member of Texas Instruments' Widebus™
Family
• UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, or Clocked Modes
• TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
• OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
• Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
• Partitioned as Two 8-Bit Transceivers With
Individual Latch Timing and Output Control,
but With a Common Clock
• LVTTL Interfaces Are 5-V Tolerant
• High-Drive GTLP Outputs (100 mA)
• LVTTL Outputs (–24 mA/24 mA)
• Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
Data-Transfer Rate and Signal Integrity in
Distributed Loads
• I_off, Power-Up 3-State, and BIAS V_CC Support
Live Insertion
• Bus Hold on A-Port Data Inputs
• Distributed V_CC and GND Pins Minimize
High-Speed Switching Noise
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DGG PACKAGE
(TOP VIEW)
1OEAB 1
1OEBA 2
V_CC 3
1A1 4
GND 5
1A2 6
1A3 7
GND 8
1A4 9
GND 10
1A5 11
GND 12
1A6 13
1A7 14
V_CC 15
1A8 16
2A1 17
GND 18
2A2 19
2A3 20
GND 21
2A4 22
2A5 23
GND 24
2A6 25
GND 26
2A7 27
V_CC 28
2A8 29
GND ³⁰
2OEAB ³¹
2OEBA 32
64 CLK
63 1LEAB
62 1LEBA
61 ERC
60 GND
59 1B1
58 1B2
57 GND
56 1B3
55 1B4
54 1B5
53 GND
52 1B6
51 1B7
50 V_CC
49 1B8
48 2B1
47 GND
46 2B2
45 2B3
44 GND
43 2B4
42 2B5
41 V_REF
40 2B6
39 GND
38 2B7
37 2B8
36 BIAS V_CC
35 _2LEAB
34 _2LEBA
33 OE
DESCRIPTION
The SN74GTLPH1655 is a high-drive, 16-bit UBT™ transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers and allows for transparent,
latched, and clocked modes of data transfer. The device provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times
faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing
(<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry.
Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using
several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 11 Ω.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, TI-OPC, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated