SN74GTLP1394 Datasheet, PDF (1/9 Pages) Texas Instruments – 2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY

SN74GTLP1394
2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SELECTABLE POLARITY
SCES286 – OCTOBER 1999
D Bidirectional Interface Between GTL+
Signal Levels and LVTTL Logic Levels
D LVTTL Interfaces Are 5-V Tolerant
D High-Drive GTL+ Outputs (100 mA)
D LVTTL Outputs (–24 mA/24 mA)
D Variable Edge-Rate Control (ERC) Input
Selects GTL+ Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity
D I_off, Power-Up 3-State, and BIAS V_CC
Support Live Insertion
D Polarity Control Selects True or
Complementary Outputs
D Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
D, DGV, OR PW PACKAGE
(TOP VIEW)
OEBY ₁
Y1 2
Y2 3
V_CC 4
A1 5
A2 6
OEAB 7
ERC 8
16 ^{BIAS V}_CC
15 GND
14 B1
13 GND
12 B2
11 GND
10 V_REF
9 T/C
description
The SN74GTLP1394 is a high-drive 2-bit 3-wire bus transceiver that provides LVTTL-to-GTL+ and
GTL+-to-LVTTL signal-level translation. It allows for transparent and inverted transparent modes of data
transfer with separate LVTTL input and LVTTL output pins. The device provides a high-speed interface between
cards operating at LVTTL logic levels and a backplane operating at GTL+ signal levels and is especially
designed to work with the Texas Instruments TSB14C01A 1394 Backplane Physical-Layer Controller.
High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of
GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, and output
edge control (OEC™). Improved GTLP OEC circuits minimize bus settling time and have been designed and
tested using several backplane models. The high drive is suitable for driving double-terminated low-impedance
backplanes using incident-wave switching.
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.
The AC specification of the SN74GTLP1394 is given only at the preferred higher noise margin GTL+, but the
user has the flexibility of using this device at either GTL (V_TT = 1.2 V and V_REF = 0.8 V) or GTL+ (V_TT = 1.5 V
and V_REF = 1 V) signal levels.
Normally, the B port operates at GTL or GTL+ levels. The A inputs, Y outputs, and control inputs are compatible
with LVTTL logic levels and are 5-V tolerant. V_REF is the reference input voltage for the B port.
This device is fully specified for live-insertion applications using I_off, power-up 3-state, and BIAS V_CC. The I_off
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V_CC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and V_CC adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright © 1999, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1