SN74GTL16622A Datasheet, PDF (1/11 Pages) Texas Instruments – 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER

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FEATURES
• Member of Texas Instruments Widebus™
Family
• OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
• D-Type Flip-Flops With Qualified Storage
Enable
• Translates Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
• Supports Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
• I_off Supports Partial-Power-Down Mode
Operation
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors on
A Port
• Distributed V_CC and GND Pins Minimize
High-Speed Noise
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
The SN74GTL16622A is an 18-bit registered bus
transceiver that provides LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL signal-level translation. This
device is partitioned as two separate 9-bit
transceivers with individual clock-enable controls and
contains D-type flip-flops for temporary storage of
data flowing in either direction. This device provides
an interface between cards operating at LVTTL logic
levels and a backplane operating at GTL/GTL+ signal
levels. Higher-speed operation is a direct result of the
reduced output swing (<1 V), reduced input threshold
levels, and OEC™ circuitry.
SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER
SCBS673F – AUGUST 1996 – REVISED APRIL 2005
DGG PACKAGE
(TOP VIEW)
OEAB 1
1A1 2
GND 3
1A2 4
1A3 5
GND 6
V_CC 7
1A4 8
GND 9
1A5 10
1A6 11
GND 12
1A7 13
1A8 14
GND 15
1A9 16
2A1 17
GND 18
2A2 19
2A3 20
GND 21
2A4 22
2A5 23
GND 24
2A6 25
V_CC 26
GND 27
2A7 28
2A8 29
GND 30
2A9 31
OEBA 32
64 CLKAB
63 1CEAB
62 1CEBA
61 1B1
60 GND
59 1B2
58 1B3
57 V_CC
56 1B4
55 1B5
54 1B6
53 GND
52 1B7
51 1B8
50 GND
49 1B9
48 2B1
47 GND
46 2B2
45 2B3
44 GND
43 2B4
42 2B5
41 2B6
40 V_REF
39 2B7
38 2B8
37 GND
36 2B9
35 2CEBA
34 2CEAB
33 CLKBA
The user has the flexibility of using this device at either GTL (V_TT = 1.2 V and V_REF = 0.8 V) or the preferred
higher noise margin GTL+ (V_TT = 1.5 V and V_REF = 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V_REF is the reference input voltage for the B port.
Data flow in each direction is controlled by the output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA)
inputs. The clock-enable (CEAB and CEBA) inputs control each 9-bit transceiver independently, which makes the
device more versatile.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2005, Texas Instruments Incorporated