SN74F175_07 Datasheet, PDF (1/12 Pages) Texas Instruments – QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR

D Contains Four Flip-Flops With Double-Rail
Outputs
D Buffered Clock and Direct Clear Inputs
D Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
description
This positive-edge-triggered flip-flop utilizes TTL
circuitry to implement D-type flip-flop logic with a
direct clear (CLR) input. Information at the data
(D) inputs meeting setup-time requirements is
transferred to outputs on the positive-going edge
of the clock pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going pulse.
When the clock (CLK) input is at either the high or
low level, the D-input signal has no effect at the
output.
SN74F175
QUADRUPLE D-TYPE FLIP-FLOP
WITH CLEAR
SDFS058B – D293, MARCH 1987 – REVISED MAY 2002
D, N, OR NS PACKAGE
(TOP VIEW)
CLR 1
1Q 2
1Q 3
1D 4
2D 5
2Q 6
2Q 7
GND 8
16 V_CC
15 4Q
14 4Q
13 4D
12 3D
11 3Q
10 3Q
9 CLK
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74F175N
SN74F175N
0°C to 70°C
SOIC – D
Tube
Tape and reel
SN74F175D
SN74F175DR
F175
SOP – NS
Tape and reel SN74F175NSR
74F175
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
CLR CLK D
L
X
X
H
↑
H
H
↑
L
H
L
X
OUTPUTS
Q
Q
L
H
H
L
L
H
Q0 Q0
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2002, Texas Instruments Incorporated
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