SN74F163A_06 Datasheet, PDF (1/14 Pages) Texas Instruments – SYNCHRONOUS 4-BIT BINARY COUNTER

SN74F163A
SYNCHRONOUS 4-BIT BINARY COUNTER
SDFS088A – MARCH 1987 – REVISED AUGUST 2001
D Internal Look-Ahead Circuitry for Fast
Counting
D, DB, OR N PACKAGE
(TOP VIEW)
D Carry Output for N-Bit Cascading
D Fully Synchronous Operation for Counting
CLR 1
CLK 2
16 V_CC
15 RCO
description
This synchronous, presettable, 4-bit binary
counter has internal carry look-ahead circuitry
for use in high-speed counting designs.
Synchronous operation is provided by having all
A3
B4
C5
D6
ENP 7
GND 8
14 Q_A
13 Q_B
12 Q_C
11 Q_D
10 ENT
9 LOAD
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the
output counting spikes that normally are associated with asynchronous (ripple-clock) counters. However,
counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four
flip-flops on the rising (positive-going) edge of CLK.
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because
presetting is synchronous, a low logic level at the load (LOAD) input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is synchronous, and a low logic level at the clear (CLR) input sets all four of the flip-flop outputs
to low after the next low-to-high transition of the clock, regardless of the levels of ENP and ENT. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to the clear input to
synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without
additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and
ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a
high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used
to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F163A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify the
operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter
(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold
times.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74F163AN
SN74F163AN
0°C to 70°C
SOIC – D
Tube
Tape and reel
SN74F163AD
SN74F163ADR
F163A
SSOP – DB
Tape and reel SN74F163ADBR
F163A
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright  2001, Texas Instruments Incorporated
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