SN74CBT3125 Datasheet, PDF (1/4 Pages) Texas Instruments – QUADRUPLE FET BUS SWITCH

D Standard ’125-Type Pinout
D 5-Ω Switch Connection Between Two Ports
D TTL-Compatible Input Levels
D Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB, DBQ), Thin Very Small-Outline (DGV),
and Thin Shrink Small-Outline (PW)
Packages
description
The SN74CBT3125 quadruple FET bus switch
features independent line switches. Each switch
is disabled when the associated output-enable
(OE) input is high.
The SN74CBT3125 is characterized for operation
from –40°C to 85°C.
FUNCTION TABLE
(each bus switch)
INPUT
OE
L
H
FUNCTION
A port = B port
Disconnect
logic diagram (positive logic)
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
Pin numbers shown are for the D, DB, DGV, and PW packages.
SN74CBT3125
QUADRUPLE FET BUS SWITCH
SCDS021E – MAY 1995 – REVISED MAY 1998
D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1B 3
2OE 4
2A 5
2B 6
GND 7
14 V_CC
13 4OE
12 4A
11 4B
10 3OE
9 3A
8 3B
DBQ PACKAGE
(TOP VIEW)
NC 1
1OE 2
1A 3
1B 4
2OE ⁵
2A ⁶
2B ⁷
GND ⁸
16 V_CC
15 4OE
14 4A
13 4B
12 3OE
11 3A
10 3B
9 NC
NC – No internal connection
3
1B
6
2B
8
3B
11
4B
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1998, Texas Instruments Incorporated
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