SN74BCT29854 Datasheet, PDF (1/7 Pages) Texas Instruments – 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

SN74BCT29854
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
• BiCMOS Process With TTL Inputs and
Outputs
• State-of-the-Art BiCMOS Design
Significantly Reduces Standby Current
• Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
• Functionally Equivalent to AMD Am29854
• High-Speed Bus Transceiver With Parity
Generator/ Checker
• Parity-Error Flag With Open-Collector
Output
• Latch for Storage of the Parity-Error Flag
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
SCBS257 – SEPTEMBER 1987 – REVISED NOVEMBER 1993
DW OR NT PACKAGE
(TOP VIEW)
OEA ₁
A1 ₂
A2 ₃
A3 4
A4 5
A5 6
A6 7
A7 8
A8 9
ERR 10
CLR 11
GND 12
24 ^V_CC
23 ^B1
22 ^B2
21 B3
20 B4
19 B5
18 B6
17 B7
16 B8
15 PARITY
14 OEB
13 LE
description
The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device
so that the buses are effectively isolated.
A 9-bit parity generator / checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector parity-error (ERR) flag. ERR can be either passed, sampled, stored, or cleared from the
latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is
transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition
which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
OEB
OEA
INPUTS
CLR
LE
Ai
∑ of H’s
Bi†
∑ of L’s
OUTPUT AND I/O
A
B PARITY ERR‡
L
H
X
X
Odd
Even
NA
NA
A
H
L
NA
H
L
X
L
NA
Odd
Even
B
NA
NA
H
L
H
L
H
H
NA
X
X
NA
NA
N–1
X
X
L
H
X
X
X
NA
NA
H
H
H
X
H
H
L
X
H
L
X
L Odd
X
X
L
H Even
NC
Z
Z
Z
H
L
H
L
L
X
X
Odd
Even
NA
NA
A
L
H
NA
NA = not applicable, NC = no change, X = don’t care
† _{Summation of low-level inputs includes PARITY along with Bi inputs.}
‡ _{Output states shown assume the ERR output was previously high.}
§ _{In this mode, the ERR output, when enabled, shows noninverted parity of the A bus.}
FUNCTION
A data to B bus and generate parity
B data to A bus and check parity
Store error flag
Clear error-flag register
Isolation§
A data to B bus and generate inverted
parity
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1993, Texas Instruments Incorporated
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