SN74AVCH2T45 Datasheet, PDF (1/23 Pages) Texas Instruments – DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

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SN74AVCH2T45
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES582D – JULY 2004 – REVISED AUGUST 2005
FEATURES
• Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
• Control Inputs V_IH/V_IL Levels Are Referenced
to V_CCA Voltage
• Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
• I/Os Are 4.6-V Tolerant
• I_off Supports Partial-Power-Down Mode
Operation
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Max Data Rates
– 500 Mbps (1.8-V to 3.3-V Translation)
– 320 Mbps (<1.8-V to 3.3-V Translation)
– 320 Mbps (Translate to 2.5 V or 1.8 V)
– 180 Mbps (Translate to 1.5 V)
– 240 Mbps (Translate to 1.2 V)
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCT OR DCU PACKAGE
(TOP VIEW)
YEP OR YZP PACKAGE
(BOTTOM VIEW)
V_CCA 1
A1 2
A2 3
GND 4
8 V_CCB
7 B1
6 B2
5 DIR
GND 4 5 DIR
A2 3 6 B2
A1 2 7 B1
V_CCA 1 8 V_CCB
DESCRIPTION/ORDERING INFORMATION
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The
SN74AVCH2T45 is optimized to operate with V_CCA/V_CCB set at 1.4 V to 3.6 V. It is operational with V_CCA/V_CCB as
low as 1.2 V. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.2 V to 3.6 V. The B
port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH2T45 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
ORDERING INFORMATION
T_A
–40°C to 85°C
PACKAGE ⁽¹⁾
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
Tape and reel
0.23-mm Large Bump – YZP (Pb-free)
ORDERABLE PART NUMBER
SN74AVCH2T45YEPR ⁽³⁾
SN74AVCH2T45YZPR ⁽³⁾
SSOP – DCT
Tape and reel SN74AVCH2T45DCTR
VSSOP – DCU
Tape and reel SN74AVCH2T45DCUR
TOP-SIDE MARKING⁽²⁾
ET2_ _ _
ET2_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
(3) Package preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated