SN74AVC16T245_08 Datasheet, PDF (1/22 Pages) Texas Instruments – 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

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SN74AVC16T245
16-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
SCES551C – FEBRUARY 2004 – REVISED AUGUST 2005
FEATURES
• Control Inputs V_IH/V_IL Levels Are Referenced
to V_CCA Voltage
• V_CC Isolation Feature – If Either V_CC Input Is at
GND, Both Ports Are in the High-Impedance
State
• Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
• Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
• I_off Supports Partial-Power-Down Mode
Operation
• I/Os Are 4.6-V Tolerant
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 8000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 16-bit noninverting bus transceiver uses two
separate configurable power-supply rails. The
SN74AVC16T245 is optimized to operate with
V_CCA/V_CCB set at 1.4 V to 3.6 V. It is operational with
V_CCA/V_CCB as low as 1.2 V. The A port is designed to
track V_CCA. V_CCA accepts any supply voltage from
1.2 V to 3.6 V. The B port is designed to track V_CCB.
V_CCB accepts any supply voltage from 1.2 V to 3.6 V.
This allows for universal low-voltage bidirectional
translation between any of the 1.2-V, 1.5-V, 1.8-V,
2.5-V, and 3.3-V voltage nodes.
DGG OR DGV PACKAGE
(TOP VIEW)
1DIR 1
1B1 2
1B2 3
GND 4
1B3 5
1B4 6
V_CCB 7
1B5 8
1B6 9
GND 10
1B7 11
1B8 12
2B1 13
2B2 14
GND 15
2B3 16
2B4 17
V_CCB 18
2B5 19
2B6 20
GND 21
2B7 22
2B8 23
2DIR 24
48 1OE
47 1A1
46 1A2
45 GND
44 1A3
43 1A4
42 V_CCA
41 1A5
40 1A6
39 GND
38 1A7
37 1A8
36 2A1
35 2A2
34 GND
33 2A3
32 2A4
31 V_CCA
30 2A5
29 2A6
28 GND
27 2A7
26 2A8
25 2OE
The SN74AVC16T245 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses
effectively are isolated.
The SN74AVC16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by V_CCA.
ORDERING INFORMATION
T_A
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
TSSOP – DGG
Tape and reel SN74AVC16T245DGGR
TVSOP – DGV
–40°C to 85°C
VFBGA – GQL
VFBGA – ZQL (Pb-free)
Tape and reel
Tape and reel
SN74AVC16T245DGVR
SN74AVC16T245GQLR
SN74AVC16T245ZQLR
TOP-SIDE MARKING
AVC16T245
WF245
WF245
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated