SN74AUP1G79 Datasheet, PDF (1/15 Pages) Texas Instruments – LOW POWER SINGLE POSITIVE EDGE TRIGGERRED D TYPE FLIP FLOP

SN74AUP1G79
LOWĆPOWER SINGLE POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP
D Available in the Texas Instruments
NanoStar and NanoFree Packages
D Low Static-Power Consumption;
I_CC = 0.9 µA Max
D Low Dynamic-Power Consumption;
C_pd = 3 pF Typ at 3.3 V
D Low Input Capacitance; C_i = 1.5 pF Typ
D Low Noise − Overshoot and Undershoot
<10% of V_CC
D I_off Supports Partial-Power-Down Mode
Operation
D Input Hysteresis Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(V_hys = 250 mV Typ at 3.3 V)
DBV OR DCK PACKAGE
(TOP VIEW)
SCES592A − JULY 2004 − REVISED SEPTEMBER 2005
D Wide Operating V_CC Range of 0.8 V to 3.6 V
D Optimized for 3.3-V Operation
D 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
D t_pd = 3.6 ns Max at 3.3 V
D Suitable for Point-to-Point Applications
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
D ESD Protection Exceeds ±5000 V With
Human-Body Model
YEP OR YZP PACKAGE
(BOTTOM VIEW)
D1
CLK 2
GND 3
5 V_CC
4Q
GND 3 4 Q
CLK 2
D 1 5 V_CC
description /ordering information
The AUP family is TI’s premier solution to the industry’s low power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire V_CC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figures 1 and 2).
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
100%
100%
80%
80%
60%
40%
3.3-V
Logic^†
60%
40%
3.3-V
L^Lo^Vg^Cic^†
20%
20%
0%
AUP
0%
AUP
† _{Single, dual, and triple gates}
Figure 1. AUP − The Lowest-Power Family
Switching Characteristics
at 25 MHz†
3.5
3
2.5
2 ^Input
Output
1.5
1
0.5
0
−0.5
0
5
10 15 20 25 ₃₀ 35 40 45
Time − ns
† _{AUP1G08 data at CL = 15 pF}
Figure 2. Excellent Signal Integrity
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the
hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2005, Texas Instruments Incorporated
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