SN74AUP1G57 Datasheet, PDF (1/16 Pages) Texas Instruments – LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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SN74AUP1G57
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
SCES503D – NOVEMBER 2003 – REVISED JUNE 2005
FEATURES
• Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
• Low Static-Power Consumption (I_CC = 0.9 µA
Max)
• Low Dynamic-Power Consumption
(C_pd = 4.3 pF Typ at 3.3 V)
• Low Input Capacitance (C_i = 1.5 pF Typ)
• Low Noise – Overshoot and Undershoot <10%
of V_CC
• I_off Supports Partial-Power-Down Mode
Operation
• Includes Schmitt-Trigger Inputs
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
• t_pd = 5.3 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
• ESD Protection Exceeds ±5000 V With
Human-Body Model
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
In1
1
GND
2
In1
1
6 In2
In1 1
6 In2
In0 ^{3 4} Y
6
5
In2
GND
V_CC
In0
2
3
5
V_CC
GND 2
In0 3
5 V_CC
4Y
GND ^{2 5}
In1 ^{1 6}
V_CC
In2
4Y
In0
3
4
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire V_CC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity,
which produces very low undershoot and overshoot characteristics.
ORDERING INFORMATION
T_A
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
Tape and reel SN74AUP1G57YEPR
–40°C to 85°C
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
Tape and reel
Tape and reel
SN74AUP1G57YZPR
SN74AUP1G57DBVR
SOT (SC-70) – DCK
Tape and reel SN74AUP1G57DCKR
SOT (SOT-553) – DRL
Reel of 4000 SN74AUP1G57DRLR
TOP-SIDE MARKING⁽²⁾
_ _ _HH_
HA7_
HH_
HH_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated