SN74AUCH16374 Datasheet, PDF (1/12 Pages) Texas Instruments – 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74AUCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES404D – JULY 2002 – REVISED MAY 2003
D Member of the Texas Instruments
Widebus Family
D Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D I_off Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max t_pd of 2.8 ns at 1.8 V
D Low Power Consumption, 20 µA Max I_CC
D ±8-mA Output Drive at 1.8 V
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 16-bit edge-triggered D-type flip-flop is
operational at 0.8-V to 2.7-V V_CC, but is designed
specifically for 1.65-V to 1.95-V V_CC operation.
DGG OR DGV PACKAGE
(TOP VIEW)
1OE ¹
1Q1 ²
1Q2 ³
GND ⁴
1Q3 ⁵
1Q4 ⁶
V_CC ⁷
1Q5 ⁸
1Q6 ⁹
GND ¹⁰
1Q7 ¹¹
1Q8 ¹²
2Q1 ¹³
2Q2 ¹⁴
GND ¹⁵
2Q3 ¹⁶
2Q4 ¹⁷
V_CC ¹⁸
2Q5 ¹⁹
2Q6 ²⁰
GND ²¹
2Q7 ²²
2Q8 ²³
2OE ²⁴
48 _1CLK
47 _1D1
46 _1D2
45 _GND
44 _1D3
43 _1D4
42 _VCC
41 _1D5
40 _1D6
39 _GND
38 _1D7
37 _1D8
36 _2D1
35 _2D2
34 _GND
33 _2D3
32 _2D4
31 _VCC
30 _2D5
29 _2D6
28 _GND
27 _2D7
26 _2D8
25 _2CLK
The SN74AUCH16374 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two
8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the
flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP – DGG
Tape and reel SN74AUCH16374DGGR AUCH16374
–40°C to 85°C TVSOP – DGV
Tape and reel SN74AUCH16374DGVR MJ374
VFBGA – GQL
Tape and reel SN74AUCH16374GQLR MJ374
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2003, Texas Instruments Incorporated
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