SN74AUC74_09 Datasheet, PDF (1/12 Pages) Texas Instruments – DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74AUC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES483A – AUGUST 2003 – REVISED MARCH 2005
FEATURES
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
• I_off Supports Partial-Power-Down Mode
Operation
• Sub-1-V Operable
• Max t_pd of 1.8 ns at 1.8 V
• Low Power Consumption, 10-µA Max I_CC
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
RGY PACKAGE
(TOP VIEW)
1
1D 2
1CLK 3
1PRE 4
1Q 5
1Q 6
7
14
13 2CLR
12 2D
11 2CLK
10 2PRE
9 2Q
8
DESCRIPTION/ORDERING INFORMATION
This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V_CC, but is designed specifically
for 1.65-V to 1.95-V V_CC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for
higher frequencies, the CLR input overrides the PRE input when they are both low.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T_A
–40°C to 85°C
QFN – RGY
PACKAGE ⁽¹⁾
Tape and reel
ORDERABLE PART NUMBER
SN74AUC74RGYR
TOP-SIDE MARKING
MS74
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
PRE
CLR
CLK
D
L
H
X
X
X
L
X
X
H
H
↑
H
H
H
↑
L
H
H
L
X
OUTPUTS
Q
Q
H
L
L
H
H
L
L
H
Q₀
Q₀
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated