SN74AUC2G86_09 Datasheet, PDF (1/13 Pages) Texas Instruments – DUAL 2-INPUT EXCLUSIVE-OR GATE

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SN74AUC2G86
DUAL 2-INPUT EXCLUSIVE-OR GATE
SCES479B – AUGUST 2003 – REVISED JANUARY 2007
FEATURES
• Available in the Texas Instruments
NanoFree™ Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
• I_off Supports Partial-Power-Down Mode
Operation
• Sub-1-V Operable
• Max t_pd of 1.7 ns at 1.8 V
DCT PACKAGE
(TOP VIEW)
• Low Power Consumption, 10-µA Max I_CC
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCU PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
1A
1
1B
2
2Y
3
8
V_CC
7
1Y
6
2B
1A 1
1B 2
2Y 3
GND 4
8
V_CC
7 _1Y
6 _2B
5 2A
GND 4 5 ^2A
2Y 3 6 2B
1B 2 7 1Y
1A 1 8 V_CC
GND
4
5
2A
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual 2-input exclusive-OR gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V
to 1.95-V V_CC operation.
The SN74AUC2G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true
form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T_A
–40°C to 85°C
PACKAGE ⁽¹⁾
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SSOP – DCT
Reel of 3000
Reel of 3000
ORDERABLE PART NUMBER TOP-SIDE MARKING⁽²⁾
SN74AUC2G86YZPR
_ _ _UH_
SN74AUC2G86DCTR
U86_ _ _
VSSOP – DCU
Reel of 3000 SN74AUC2G86DCUR
U86_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated