SN74AUC2G34 Datasheet, PDF (1/13 Pages) Texas Instruments – Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation

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SN74AUC2G34
DUAL BUFFER GATE
SCES514A – NOVEMBER 2003 – REVISED MARCH 2006
FEATURES
• Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
• I_off Supports Partial-Power-Down Mode
Operation
• Sub-1-V Operable
• Max t_pd of 1.6 ns at 1.8 V
• Low Power Consumption, 10 µA at 1.8 V
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
1A
1
6
1Y
DCK PACKAGE
(TOP VIEW)
1A 1 6 1Y
DRL PACKAGE
(TOP VIEW)
1A 1
6 1Y
YEP PACKAGE
(BOTTOM VIEW)
2A 3 4 2Y
GND
2
5
V_CC GND
2
5
V_CC GND 2
5 V_CC
GND 2
V 5
CC
2A 3 4 2Y
2A 3
4 2Y
1A 1 6 1Y
2A
3
4
2Y
DESCRIPTION/ORDERING INFORMATION
This dual buffer gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC
operation.
The SN74AUC2G34 performs the Boolean function Y = A in positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER TOP-SIDE MARKING⁽²⁾
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Tape and reel
SN74AUC2G34YEPR
SN74AUC2G34YZPR
_ _ _U9_
SOT-563 – DRL
Tape and reel SN74AUC2G34DRLR
U9_
SOT-23 – DBV
Tape and reel SN74AUC2G34DBVR
U34_
SC-70 – DCK
Tape and reel SN74AUC2G34DCKR
U9_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated