SN74AUC2G126 Datasheet, PDF (1/12 Pages) Texas Instruments – DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

D Available in the Texas Instruments
NanoStar and NanoFree Packages
D Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D I_off Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max t_pd of 1.9 ns at 1.8 V
D Low Power Consumption, 10 µA at 1.8 V
D ±8-mA Output Drive at 1.8 V
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN74AUC2G126
DUAL BUS BUFFER GATE
WITH 3ĆSTATE OUTPUTS
SCES533A − DECEMBER 2003 − REVISED FEBRUARY 2004
DCT OR DCU PACKAGE
(TOP VIEW)
1OE 1
1A 2
2Y 3
GND 4
8 V_CC
7 2OE
6 1Y
5 2A
YEP OR YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 2A
2Y 3 6 1Y
1A 2 7 2OE
1OE 1 8 V_CC
description/ordering information
This dual bus buffer gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V
V_CC operation.
The SN74AUC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the
associated output-enable (OE) input is low.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
−40°C to 85°C
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Tape and reel SN74AUC2G126YEPR
Tape and reel SN74AUC2G126YZPR
_ _ _UN_
SSOP − DCT
Tape and reel SN74AUC2G126DCTR U26_ _ _
VSSOP − DCU
Tape and reel SN74AUC2G126DCUR UN_
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at}
www.ti.com/sc/package.
‡ _{DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.}
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2004, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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