SN74AUC2G08 Datasheet, PDF (1/11 Pages) Texas Instruments – DUAL 2 - INPUT POSITIVE - AND GATE

SN74AUC2G08
DUAL 2ĆINPUT POSITIVEĆAND GATE
D Available in the Texas Instruments
NanoStar and NanoFree Packages
D Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D I_off Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max t_pd of 1.5 ns at 1.8 V
D Low Power Consumption, 10 µA at 1.8 V
D ±8-mA Output Drive at 1.8 V
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SCES477A − AUGUST 2003 − REVISED NOVEMBER 2003
DCT OR DCU PACKAGE
(TOP VIEW)
1A 1
1B 2
2Y 3
GND 4
8 V_CC
7 1Y
6 2B
5 2A
YEP OR YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 2A
2Y 3 6 2B
1B 2 7 1Y
1A 1 8 V_CC
description/ordering information
This dual 2-input positive-AND gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V
to 1.95-V V_CC operation.
The SN74AUC2G08 performs the Boolean function Y + A • B or Y + A ) B in positive logic.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
−40°C to 85°C
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Tape and reel
SN74AUC2G08YEPR
SN74AUC2G08YZPR
_ _ _UE_
SSOP − DCT
Tape and reel SN74AUC2G08DCTR U08_ _ _
VSSOP − DCU
Tape and reel SN74AUC2G08DCUR U08_
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available}
at www.ti.com/sc/package.
‡ _{DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.}
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and
one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2003, Texas Instruments Incorporated
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