SN74AUC1GU04_10 Datasheet, PDF (1/12 Pages) Texas Instruments – SINGLE INVERTER GATE

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SN74AUC1GU04
SINGLE INVERTER GATE
SCES371L – SEPTEMBER 2001 – REVISED APRIL 2007
FEATURES
• Available in the Texas Instruments
NanoFree™ Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
• Sub-1-V Operable
• Max t_pd of 2.4 ns at 1.8 V
• Low Power Consumption, 10-µA Max I_CC
• ±8-mA Output Drive at 1.8 V
• Unbuffered Output
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRY PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
NC
1
A
2
5
NC
V_CC
A
GND
1
2
3
5
4
V_CC
Y
GNNCAD_PR^{321EV465IEWVYNCCC}
GND
A
DNU
34
2
15
Y
V_CC
GND
3
4
Y
DNU - Do not use
NC – No internal connection
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single inverter gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC
operation.
The SN74AUC1GU04 contains one inverter with an unbuffered output and performs the Boolean function Y = A.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
ORDERING INFORMATION
T_A
–40°C to 85°C
PACKAGE ^{(1) (2)}
NanoFree™ – WCSP
(DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
SON – DRY
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
Reel of 3000
Reel of 5000
Reel of 300
Reel of 300
ORDERABLE PART
NUMBER
SN74AUC1GU04YZPR
SN74AUC1GU04DRYR
SN74AUC1GU04DBVR
SN74AUC1GU04DCKR
TOP-SIDE MARKING⁽³⁾
_ _ _UD_
PREVIEW
UU4_
UD_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2007, Texas Instruments Incorporated